Document Details

Document Type : Thesis 
Document Title :
Fabrication and Characterization of High-k Gate Dielectrics for MOS Devices
تصنيع وتوصيف بوابات عالية العزل لنبائط أشباه الموصلات
 
Subject : physics department 
Document Language : Arabic 
Abstract : The gate stack used in current-generation of most MOS (Metal-Oxide-Semiconductor) devices consists of silicon, an insulating layer of silicon dioxide, and a metallic gate electrode made of polysilicon. For future electronics the communities search for new dielectric materials that replace silicon dioxide. Today, most of MOS devices are decreasing in size but this decrease is has a limit. As the thickness of silicon dioxide scales below 3 nm, the gate leakage current; due to tunneling take place leading to failure of devices and significant heat dissipation. To overcome the thickness limits problem, control power consumption, and enhance performance, a new insulating layer with high dielectric constant (high-k) should be found. The aim of this work is the preparation and investigation of new high-k dielectric materials that can be used in MOS devices and pushing the electronic devices into smaller sizes and great performance. Our choices of techniques of deposition are thermal evaporation, e‐beam evaporation systems, and rf‐sputtering which combine clean UHV conditions with a high versatility in new materials growing. The obtained new high k-materials has good thermodynamic stability with Si and large band gap about 4.7 eV, good film morphology (no grain boundaries; i.e nanograins structures) and good compatibility with metal gate electrode with high‐quality interface (low defect density). 
Supervisor : Prof. FAHAD M. AL-MARZOUKI 
Thesis Type : Master Thesis 
Publishing Year : 1434 AH
2013 AD 
Co-Supervisor : dr. 
Added Date : Monday, October 21, 2013 

Researchers

Researcher Name (Arabic)Researcher Name (English)Researcher TypeDr GradeEmail
سعيد علي الزهرانيAl zahrani, Saeed AliResearcherMaster 

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 36164.pdf pdf 

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